Login / Signup
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation.
Adán Kohler
Gert Schley
Martin Radetzki
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2010)
Keyphrases
</>
fault tolerant
network on chip
interconnection networks
fault tolerance
routing algorithm
network simulator
distributed systems
multi processor
load balancing
data transfer
database
power dissipation
multistage
ad hoc networks
multipath
shared memory
digital libraries
image processing