A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform.
Jeong Hun KimSuki KimKwang-Hyun BaekPublished in: IEICE Trans. Inf. Syst. (2010)
Keyphrases
- low power
- vlsi architecture
- low cost
- power consumption
- high speed
- cmos technology
- real time
- wireless transmission
- mixed signal
- high power
- single chip
- design considerations
- digital signal processing
- nm technology
- mobile phone
- low power consumption
- communication protocol
- logic circuits
- wifi
- power reduction
- model checking
- signal processor
- data flow
- ubiquitous computing
- embedded systems
- vlsi circuits