A Low Power cryogenic CMOS ROIC Design for 512 × 512 IRFPA.
Hongliang ZhaoYiqiang ZhaoYiwei SongJun LiaoJunfeng GengPublished in: J. Circuits Syst. Comput. (2013)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- high speed
- cmos technology
- vlsi architecture
- low power consumption
- power dissipation
- ultra low power
- logic circuits
- digital signal processing
- mixed signal
- nm technology
- focal plane
- vlsi circuits
- image sensor
- design process
- cmos image sensor
- gate array
- high power
- power reduction
- analog to digital converter
- wireless transmission
- parallel processing
- video sequences
- image processing