A Finite Field Processor Employing Dual Parallel Datapath for High-Speed/Low-Power RS-ECC Applications.
Hyung-Joon KwonYoung-Beom JangBangwon LeePublished in: IEEE International Conference on Multimedia and Expo (III) (2000)
Keyphrases
- low power
- high speed
- single chip
- gate array
- power consumption
- wireless transmission
- high power
- low cost
- frame rate
- parallel processing
- real time
- low power consumption
- logic circuits
- digital signal processing
- cmos technology
- mixed signal
- vlsi circuits
- error correction
- image sensor
- parallel programming
- power reduction
- computer architecture
- signal processor