Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN.
Anam ZamanOsman HasanPublished in: ISSoC (2014)
Keyphrases
- network on chip
- formal verification
- power dissipation
- interconnection networks
- routing algorithm
- cmos technology
- power consumption
- model checking
- multi processor
- network simulator
- low power
- packet switched
- high speed
- fault tolerant
- data transfer
- wireless sensor networks
- multi core processors
- finite state machines
- multipath
- parallel algorithm
- multistage
- message passing
- image sensor
- design methodology
- parallel architectures
- data flow
- image processing