Performance evaluation of instruction systolic array processors.
Leo Chin SimGraham LeedhamHeiko SchröderPublished in: ICARCV (2002)
Keyphrases
- systolic array
- parallel architecture
- instruction set
- reconfigurable architecture
- data flow
- parallel processing
- hardware implementation
- shared memory
- parallel algorithm
- memory hierarchy
- multimedia
- instructional design
- distributed memory
- parallel implementation
- application specific
- cooperative
- level parallelism
- floating point
- computer assisted instruction
- database
- computer technology
- multiprocessor systems
- databases