High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware.
Sujoy Sinha RoyAndrea BassoPublished in: IACR Cryptol. ePrint Arch. (2020)
Keyphrases
- instruction set
- high speed
- computer architecture
- dedicated hardware
- floating point
- embedded systems
- application specific
- real time
- floating point arithmetic
- ibm power processor
- level parallelism
- instruction set architecture
- memory access
- hardware implementation
- low cost
- multi dimensional
- computer systems
- general purpose
- information systems
- databases