A code decompression architecture for VLIW processors.
Yuan XieWayne H. WolfHaris LekatsasPublished in: MICRO (2001)
Keyphrases
- instruction set
- level parallelism
- parallel architecture
- real time
- management system
- code generation
- instruction set architecture
- data flow
- image compression
- processing elements
- software architecture
- multithreading
- industry standard
- source code
- neural network
- shared memory
- parallel computing
- compression scheme
- multi core processors
- multi processor
- instruction scheduling