A Low-Power Parallel Architecture for Linear Feedback Shift Registers.
Xinmiao ZhangPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
- low power
- parallel architecture
- power consumption
- high speed
- low cost
- high power
- parallel processing
- low power consumption
- single chip
- systolic array
- hardware implementation
- high level synthesis
- digital signal processing
- vlsi circuits
- vlsi architecture
- distributed memory
- logic circuits
- shared memory
- wireless transmission
- image sensor
- parallel implementation
- gate array
- nm technology
- delay insensitive
- mixed signal
- cmos technology