Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger.
Christian HinkelbeinAndrei KhomichAndreas KugelReinhard MännerMatthias MüllerPublished in: FPGA (2004)
Keyphrases
- feature extraction
- execution speed
- real time
- learning algorithm
- computational complexity
- dedicated hardware
- significant improvement
- computational cost
- computationally efficient
- theoretical analysis
- data structure
- efficient implementation
- computer vision
- image segmentation
- discriminant analysis
- software implementation