An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding.

Saeed Sharifi Tehrani Shie Mannor Warren J. Gross

Published in: SiPS (2007)

Keyphrases

hardware design
real time
hardware architecture
parallel execution
low density parity check
parallel processing
wireless communication
hardware implementation
parallel implementation
computer architecture
processing units
parallel computers
processing elements
master slave
level parallelism