A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC.
Hyeok-Ki HongWan KimHyun-Wook KangSun-Jae ParkMichael ChoiHo-Jin ParkSeung-Tak RyuPublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- error tolerant
- non binary
- graph matching
- cmos technology
- constraint satisfaction problems
- analog to digital converter
- silicon on insulator
- subgraph isomorphism
- frequent pattern mining
- arc consistency
- low power
- metal oxide semiconductor
- pattern recognition
- huge number
- association patterns
- power consumption
- constraint satisfaction