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Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design.
Francesco Sgherzi
Alberto Parravicini
Marco Siracusa
Marco Domenico Santambrogio
Published in:
CoRR (2021)
Keyphrases
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user defined
neural network
query processing
design process
hardware design
fpga implementation
image processing
high speed
random walk
structured data
main memory
hardware implementation
directed acyclic graph
single chip
digital signal processing
reconfigurable hardware