Login / Signup

Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers.

Nobuhiro TomabechiTeruki Ito
Published in: ICECS (2001)
Keyphrases
  • high speed
  • database
  • design process
  • single chip
  • real time
  • case study
  • user interface
  • software architecture
  • digital signature
  • memory management