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Formal Verification Of Self-Testing Properties Of Combinational Circuits.

Kazuo KawakuboKoji TanakaHiromi Hiraishi
Published in: Asian Test Symposium (1996)
Keyphrases
  • formal verification
  • model checking
  • model checker
  • bounded model checking
  • automated verification
  • asynchronous circuits
  • symbolic model checking
  • high speed
  • delay insensitive
  • neural network