Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.
Geetam Singh TomarMarcus Lloyde GeorgePublished in: Wirel. Pers. Commun. (2018)
Keyphrases
- high end
- processing units
- hardware implementation
- field programmable gate array
- response time
- hardware software
- resource utilization
- floating point
- data flow
- heterogeneous computing
- low latency
- real time
- hardware architecture
- fpga technology
- vlsi implementation
- pipelined architecture
- floating point arithmetic
- software implementation
- hardware design
- low cost
- management system