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A 6.15-10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With "Phase Reset" Scheme.

Wenbo XiaoQiwei HuangHamed MosalamChenchang ZhanZhiqun LiQuan Pan
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2022)
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