TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC.
Wolfgang KlingaufHagen GädkeRobert GünzelPublished in: DATE (2006)
Keyphrases
- hardware software
- hw sw
- design methodology
- field programmable gate array
- hardware and software
- embedded systems
- hardware design
- hardware software co design
- hardware implementation
- multi layer
- high performance computing
- multi core processors
- management system
- database
- low cost
- parallel computing
- efficient implementation
- neural network
- real time