A 5.5 GHz low-power PLL using 0.18-µm CMOS technology.

Jeng-Han Tsai Shao-Wei Huang Jian-Ping Chou

Published in: RWS (2014)

Keyphrases

low power
cmos technology
high speed
power consumption
clock frequency
low cost
low voltage
single chip
power dissipation
low power consumption
mixed signal
digital signal processing
energy efficiency
image sensor
power management
image enhancement
power reduction
signal processing