FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers.
Bogdan MatasaruTudor JebeleanPublished in: FPL (2000)
Keyphrases
- fpga implementation
- hardware implementation
- learning algorithm
- computational complexity
- np hard
- optimal solution
- detection algorithm
- information systems
- worst case
- preprocessing
- search space
- k means
- objective function
- dynamic programming
- image processing algorithms
- neural network
- machine learning
- expectation maximization
- simulated annealing
- open source
- probabilistic model
- real time