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Divide-by-16/17 dual modulus prescaler design with enhanced speed in a 180nm CMOS technology.

Uma NirmalV. K. Jain
Published in: Int. J. Comput. Aided Eng. Technol. (2021)
Keyphrases
  • cmos technology
  • low power
  • power dissipation
  • high speed
  • power consumption
  • spl times
  • real time
  • user interface
  • design process
  • case study
  • low cost
  • mixed signal
  • single chip
  • low voltage
  • silicon on insulator