Architecture design of low-power and low-cost CAVLC decoder for H.264/AVC.
Han-Jung HuangChih-Peng FanPublished in: APCCAS (2008)
Keyphrases
- low power
- low cost
- video coding standard
- video codec
- video coding
- variable length coding
- bit rate
- decoding process
- deblocking filter
- error resilient
- coding efficiency
- coding method
- low complexity
- motion compensation
- rate distortion
- motion compensated
- bitstream
- error concealment
- motion vectors
- macroblock
- video compression
- distributed video coding
- single chip
- discrete cosine transform
- coding scheme
- rate allocation
- low bit rate
- image coding
- video quality
- motion estimation
- visual quality
- inter frame
- intra prediction
- compressed video
- entropy coding
- rate control
- low power consumption
- computational complexity
- high speed
- source coding
- real time
- error resilience
- digital camera
- wyner ziv
- power consumption
- error propagation
- video streaming
- temporal correlation
- mode decision
- logic circuits
- video data
- image sensor
- scalable video
- transform domain
- video transmission
- rfid tags
- image transmission
- compressed domain
- cmos technology
- video streams