Login / Signup

Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique.

Dongjin LeeJaewon SongJongha ShinSanghoon HwangMinkyu SongTad Wysocki
Published in: ECCTD (2007)
Keyphrases
  • analog to digital converter
  • circuit design
  • email
  • case study
  • low cost
  • high speed
  • mathematical model
  • power consumption
  • design principles
  • low power
  • design methodology
  • power supply
  • data conversion