A fast parallel reed-solomon decoder on a reconfigurable architecture.

Arezou Koohi Nader Bagherzadeh Chengzi Pan

Published in: CODES+ISSS (2003)

Keyphrases

bit errors
reed solomon
reconfigurable architecture
error correction
systolic array
error control
parallel architecture
data flow
parallel implementation
parallel processing
distributed memory
channel coding
turbo codes