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Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge.
Shaoyi Wang
Published in:
Great Lakes Symposium on VLSI (1997)
Keyphrases
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power reduction
logic circuits
low power
power consumption
power dissipation
high speed
low cost
cmos technology
delay insensitive
power saving
chip design
focal plane
digital signal processing
energy saving
energy efficiency
real time
distributed systems
random access memory