A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation.
Hedi WangZengwei WangYaolei LiChen TangJinxu GaoHuazhong YangYongpan LiuPublished in: A-SSCC (2023)
Keyphrases
- coarse grained
- fpga implementation
- processing elements
- hardware implementation
- fine grained
- parallel computers
- signal processing
- field programmable gate array
- massively parallel
- shared memory
- image processing algorithms
- hardware architecture
- parallel computing
- efficient implementation
- digital signal processor
- parallel architecture
- protein sequences
- linear algebra
- parallel algorithm
- low cost
- high level
- random access
- access control
- image processing
- embedded systems
- message passing
- parallel processors
- associative memory
- bit rate