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An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS.
Wei Guo
Shubin Liu
Zhangming Zhu
Published in:
Microelectron. J. (2016)
Keyphrases
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high speed
analog to digital converter
shift register
low power
delay insensitive
sar images
sar imagery
low voltage