A CMOS gate array with dynamic-termination GTL I/O circuits.

Junya Kudoh Toshiro Takahashi Yukio Umada Masaharu Kimura Shigeru Yamamoto Youichi Ito

Published in: ICCD (1995)

Keyphrases

gate array
low power
high speed
circuit design
analog vlsi
delay insensitive
dynamic environments
logic circuits
vlsi circuits
low cost
input output
power consumption
main memory
power dissipation
asynchronous circuits
chip design
floating gate