Variation aware low power buffered interconnect design.
Ashok NarasimhanRamalingam SridharPublished in: SoCC (2009)
Keyphrases
- low power
- high speed
- power dissipation
- power consumption
- single chip
- low cost
- vlsi architecture
- low power consumption
- gate array
- digital signal processing
- cmos technology
- mixed signal
- logic circuits
- wireless transmission
- vlsi circuits
- real time
- ultra low power
- power reduction
- design process
- high power
- design methodology
- nm technology
- image processing