A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture.

Kai-Ting Shr Yu-Cheng Chang Chu-Yi Lin Yuan-Hao Huang

Published in: A-SSCC (2011)

Keyphrases

real time
bit parallel
management system
neural network
low complexity
network architecture
design considerations
euler number
pattern matching
floating point
fpga implementation
table lookup