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Efficient ASIC Architecture for Low Latency Classic McEliece Decoding.

Daniel FallnichChristian LaniusShutao ZhangTobias Gemmeke
Published in: IACR Trans. Cryptogr. Hardw. Embed. Syst. (2024)
Keyphrases
  • low latency
  • real time
  • high speed
  • highly efficient
  • virtual machine
  • hardware implementation
  • hardware architecture
  • high throughput
  • high bandwidth
  • massive scale
  • databases
  • cost effective