A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements.
M. RahimiM. B. Ghaznavi-GhoushchiPublished in: Microelectron. J. (2019)
Keyphrases
- low power
- high speed
- tree structure
- power consumption
- power dissipation
- high power
- tree representation
- low cost
- single chip
- power reduction
- tree structures
- data structure
- frequent patterns
- cmos technology
- real time
- logic circuits
- vlsi architecture
- digital signal processing
- quadtree
- low power consumption
- vlsi circuits
- markov tree
- binary tree
- r tree
- xml documents
- neural network
- data sets