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A merged 2.5 V and 3.3 V 0.25-μm CMOS technology for ASICs.

Isik C. KizilyalliR. HuangD. HwangH. VaidyaBrittin KaneRobert AshtonS. KuehneX. DengM. TwifordDavid ShuttleworthE. MartinX. LiM. J. Thoma
Published in: CICC (1998)
Keyphrases
  • cmos technology
  • low power
  • spl times
  • low voltage
  • parallel processing
  • power consumption
  • power dissipation
  • mixed signal
  • low cost
  • high speed
  • image sensor
  • embedded systems
  • field programmable gate array