An Analytical Model Proposed for Evaluating Efficiency of Partitioning Code in Hybrid Architectures Based on DSP and FPGA.
Éricles Rodrigues SousaLuis MeloniPublished in: HPCC (2011)
Keyphrases
- analytical model
- high speed
- real time image processing
- verilog hdl
- signal processing
- analytical models
- digital signal processing
- systolic array
- digital signal processors
- simulation model
- hardware implementation
- digital signal
- source code
- texas instruments
- computational complexity
- real time
- bit error rate
- graph partitioning
- data flow
- high efficiency
- wireless communication
- operating system
- low cost