A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL.

Young-Sang Kim Seon-Kyoo Lee Hong-June Park Jae-Yoon Sim

Published in: IEEE J. Solid State Circuits (2011)

Keyphrases

high speed
clock frequency
concurrency control
neural network
data objects
multiresolution
high frequency
digital media
preprocessing phase
fine granularity
data structure
frequency band