A new low-power, low-area, parallel prefix Sklansky adder with reduced inter-stage connections complexity.
Mahta MoghaddamM. B. Ghaznavi-GhoushchiPublished in: EUROCON (2011)
Keyphrases
- low power
- logic circuits
- power consumption
- low cost
- high speed
- low power consumption
- power dissipation
- bit parallel
- single chip
- high power
- digital signal processing
- wireless transmission
- parallel processing
- cmos technology
- vlsi circuits
- real time
- computational complexity
- power reduction
- mixed signal
- vlsi architecture
- image sensor
- signal processing
- gate array