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A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology.
Zhongkai Wang
Minsoo Choi
Paul Kwon
Kyoungtae Lee
Bozhi Yin
Zhaokai Liu
Kwanseo Park
Ayan Biswas
Jaeduk Han
Sijun Du
Elad Alon
Published in:
VLSI Technology and Circuits (2022)
Keyphrases
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cmos technology
low power
high speed
spl times
power consumption
low voltage
parallel processing
low cost
silicon on insulator
power dissipation
mixed signal
real time
computer vision
case study
digital images
signal processing