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A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery.

Koichi YamaguchiYoshihiko HoriKeiichi NakajimaKazumasa SuzukiMasayuki MizunoHiroshi Hayama
Published in: IEEE J. Solid State Circuits (2009)
Keyphrases
  • noise tolerant
  • high speed
  • instance based learning algorithms
  • noisy data
  • frame rate
  • statistical queries
  • nearest neighbor
  • power consumption
  • data sets
  • learning algorithm
  • cost function
  • small number