Implementation of a reconfigurable architecture of discrete wavelet packet transform with three types of multipliers on FPGA.
Mohsen Amiri FarahaniSaeid MirzaeiHossein Amiri FarahaniPublished in: CCECE (2011)
Keyphrases
- reconfigurable architecture
- wavelet packet transform
- systolic array
- hardware implementation
- parallel architecture
- efficient implementation
- shift invariant
- wavelet packet
- wavelet coefficients
- low cost
- texture features
- feature extraction
- data flow
- image compression
- markov random field
- denoising
- wavelet transform
- training data