FPGA hardware implementation of Q-learning algorithm with low resource consumption.
Xiaojuan LiuJietao DiaoNan LiPublished in: PRIS (2022)
Keyphrases
- hardware implementation
- resource consumption
- field programmable gate array
- dedicated hardware
- fpga implementation
- signal processing
- efficient implementation
- software implementation
- hardware architecture
- solution quality
- resource allocation
- data transfer
- hardware design
- image processing algorithms
- response time
- fpga technology
- pipelined architecture
- reconfigurable hardware
- fpga device
- general purpose processors
- machine learning
- parallel architecture
- pattern recognition
- processing times
- scheduling algorithm
- simulated annealing
- xilinx virtex
- image processing
- real time