A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications.
Hyung-Joon KwonKwyro LeePublished in: ISLPED (1997)
Keyphrases
- low power
- power consumption
- high speed
- vlsi architecture
- low cost
- cmos technology
- nm technology
- single chip
- mixed signal
- wireless transmission
- data flow
- real time
- vlsi circuits
- low power consumption
- high power
- logic circuits
- general purpose
- power saving
- digital signal processing
- parallel architecture
- error correction
- power reduction
- low density parity check
- gate array