Implementation of the compression function for selected SHA-3 candidates on FPGA.
Ashkan Hosseinzadeh NaminM. Anwar HasanPublished in: IPDPS Workshops (2010)
Keyphrases
- hardware implementation
- image compression
- real time
- hardware architectures
- high speed
- signal processing
- hardware architecture
- reconfigurable hardware
- dedicated hardware
- software implementation
- fpga implementation
- fpga hardware
- database
- fpga technology
- fpga device
- hardware design
- randomly selected
- computational complexity
- multiscale
- information systems
- genetic algorithm