An Approach to Enhance Loop Performance for Multicluster VLIW DSP Processor.
Yangzhao YangNaijie GuKaixin RenBingqing HuPublished in: ARCS Workshops (2014)
Keyphrases
- high speed
- signal processing
- systolic array
- digital signal
- level parallelism
- parallel processing
- digital signal processor
- digital signal processing
- low cost
- multiprocessor systems
- feedback loop
- single chip
- real time image processing
- instruction set
- real world
- wireless sensor networks
- image processing
- information retrieval