An FPGA-based reconfigurable IPSec AH core with efficient implementation of SHA-3 for high speed IoT applications.
Muzaffar RaoThomas NeweIan Andrew GroutAvijit MathurPublished in: Secur. Commun. Networks (2016)
Keyphrases
- efficient implementation
- hardware implementation
- high speed
- field programmable gate array
- hardware architecture
- hardware design
- low power
- management system
- efficient processing
- active set
- image processing algorithms
- reconfigurable architecture
- real time
- high speed networks
- highly parallel
- location information
- cloud computing
- application specific
- smart camera
- network security
- low cost