Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor.
Jean-Francois CollardDaniel M. LaveryPublished in: CGO (2003)
Keyphrases
- memory hierarchy
- computer architecture
- computing power
- multi core processors
- main memory
- embedded processors
- processor core
- memory access
- memory subsystem
- secondary storage
- multithreading
- single instruction multiple data
- cache misses
- memory management
- shared memory multiprocessors
- database operations
- single chip
- operating system
- shared memory multiprocessor
- read write
- hit rate
- instruction set
- prefetching
- data access
- database workloads
- computer systems
- query processing
- optimization strategies
- massively parallel
- parallel processing
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