A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine.
Hisashi SasakiPublished in: DATE (1999)
Keyphrases
- formal semantics
- state machine
- state machines
- fault tolerant
- logical language
- modelling language
- finite state machines
- modeling language
- operational semantics
- formal language
- hardware description language
- first order logic
- database systems
- ontology languages
- integrated circuit
- theorem prover
- semantic web
- hardware implementation
- case study
- owl dl ontology