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A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers.
Jianhui Wu
Jiafeng Zhu
YingCheng Xia
Na Bai
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2014)
Keyphrases
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multiple stages
neural network
database systems
parallel processing
multiple objects
genetic algorithm
digital libraries
evolutionary algorithm
peer to peer
parallel computing
multiple independent