NoC-based fault-tolerant cache design in chip multiprocessors.

Abbas BanaiyanMofrad Gustavo Girão Nikil D. Dutt

Published in: ACM Trans. Embed. Comput. Syst. (2014)

Keyphrases

fault tolerant
fault tolerance
evolvable hardware
distributed systems
low cost
load balancing
high availability
state machine
single chip
high speed
multithreading
safety critical
low power
multistage
fault isolation
network on chip
memory subsystem
ibm power processor