An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking.

Zhen Luo Margaret Martonosi Pranav Ashar

Published in: VLSI Design (2000)

Keyphrases

hardware architecture
layout design
hardware implementation
hardware architectures
signal processing
integer programming
associative memory
endpoints
block matching motion estimation
tunnel boring machine
real time
neural network
field programmable gate array