Novel Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2D Inverse DWT.
Goran SavicVladimir M. RajovicPublished in: J. Circuits Syst. Comput. (2019)
Keyphrases
- memory efficient
- hardware architecture
- lifting scheme
- wavelet transform
- discrete wavelet transform
- hardware implementation
- multiresolution
- image compression
- iterative deepening
- hardware architectures
- wavelet domain
- external memory
- subband
- processing elements
- multiple sequence alignment
- field programmable gate array
- associative memory
- real time
- filter bank
- multiscale
- high frequency
- wavelet coefficients
- lossy compression
- integral image
- computer vision
- lossless compression
- spatial domain
- signal processing
- pattern recognition